A Diagram for Graphing the Dynamic Behaviour of RTL Circuits

This part of the lesson introduces a simple diagram for representing the time evolution of the execution of a circuit at Register Transfer Level.

A multi-operation RTL circuit

The only difference between the circuit below and the previous ones, is that this executes two operations within the two registers: an exponentiation to the power of two, and an increment. Therefore, given input 'x', we expect output to be 'x' to the power of two, plus one. Note that the multiply chip does not feature the whole circuit down to nand gates, as it would be extremely complex: it 'cheats' with an ad hoc component and an artificial fixed propagation delay.

Graphing the dynamic behaviour of RTL circuits

The graph has the cycles on the x axis, that are read from left to right, and the inputs given to the circuits on the y axis, that are read from top to bottom. In a nutshell, it keeps track of which input was being processed by the circuit at each cycle. At the crossing between the cycle and the input we are considering, we write the operation that has been carried on that input in that cycle.

Let us now compile the graph while manually advancing the simulation. Let us pause it, inspect the clock signal, the input and the output, and enable the registers. Let's set the first input at zero, write it in the table, and advance by one clock cycle. We will see that though the input has been sampled by the rising edge of the clock, the output has not updated yet, as it will at the next rising edge. Remember that we consider the beginning of a clock cycle as its rising edge, and the end of it at the step just before the next rising edge.

At this point the operation of the circuit has been done on the first input, that is exponentiation and increment, so we write it down under cycle 1. We can therefore write the new output, let's say 5, and advance by one cycle.

We can see the result for the first input being sampled, and we can compile the diagram with the operation at cycle 2. Then we start over again. New input, write the input in the table, advance one cycle and write the operation on the table.

After a few steps we have a compiled table, that we can read in the following manner. What operation was done to input of value 5 in cycle 2? We can read exponentiation and increment. What operation was done on input of value 12 at cycle 4? We here read none. The reason why we have values only on the diagonal, is because the present circuit can only process one input at the time, which means that each input is processed in one clock cycle from beginning to end. For now, let us keep how this diagram is constructed in mind, but let us not forget the original topic: that of propagation delays and the constraint they set on the clock speed.

The 24/7 Laundry Analogy

Imagine being the engineer who designed this circuit,and that wants to process inputs faster. How can we modify the RTL circuit so that it maintains functionality but speeds calculations? Let us try to get to an answer with an analogy.

Imagine being the manager of a laundry business open 24/7, which offers a washing machine which takes 1.45 hours to operate, a dryer which takes 1.30 hours and an ironer which takes 2 hours. One client comes in, uses the room with the three machines and then leaves, much like one input of the circuit above, which enters the input register, is processed, exiting from the output register. With this organization each client keeps the room busy for 5.15 hours, and we can see a diagram similar to what we compiled before, in which each time frame contains the entire cleaning process of only one client. How then can we optimize the profits of the laundry business?

Daily activity of a 24/7 laundry.